1. Field of the Invention
The present invention relates to integrated circuits, and more specifically to a semiconductor integrated circuit having a stack of conducting layers separated by insulating layers.
2. Description of Related Art
In conventional integrated circuits, it is necessary to establish electrical connections between conducting metallized layers that are on different levels and separated by one or more insulating layers. Two conducting layers are conventionally electrically connected using holes that are provided in the insulating layer and filled with metal, such a connection being known as a xe2x80x9cviaxe2x80x9d. One way of producing such integrated circuits is through a process known as the xe2x80x9cDamascenexe2x80x9d process. A first insulating layer is deposited on a metallization layer of level n. The holes are etched through the insulating layer, and the metal for the via is deposited and polished until it is level with the upper surface of the insulating layer.
Then, a new insulating layer is deposited on the formed via of level n and the trenches for the lines are etched. The metal for the lines of the metallization layer of level n+1 is deposited, and then polished until level with the upper surface of the insulating layer. The Damascene process is well suited for producing copper lines and vias because, although copper has advantageous electrical properties for narrow lines, it cannot be etched at ambient temperature. Additionally, the Damascene process can be used with the metals more commonly used to form lines and vias.
In a xe2x80x9cdouble Damascenexe2x80x9d process, the metal is deposited in both the vias and the lines and then polished. A stop layer, usually made of nitride, is provided between an insulating layer of level n and the metallization level n+1. In order to obtain the final structure, there must be excellent etching selectivity for the oxide of the insulating layer with respect to the nitride.
In order to increase the density of integrated circuits, attempts have been made to reduce the width of the metal lines and of the dielectric material separating metal lines. However, the electrical capacitance between two adjacent metal lines is inversely proportional to the distance separating them. Thus, by reducing this distance to increase the density of the circuit, the interline capacitance is increased. This is a problem because it causes an increase in the propagation constant of the electrical signal in the lines, xcfx84=RC (R being the resistance of the metal line and C being the interline capacitance), as well as in an increase in the parasitic coupling between two electrical signals propagating in two adjacent lines (i.e., the crosstalk effect).
The interline capacitance is proportional to the permittivity coefficient xe2x80x9ckxe2x80x9d of the dielectric material that is used, so there is a tendency to use dielectric materials having a low permittivity coefficient xe2x80x9ckxe2x80x9d. For example, dielectric organic polymers having permittivity coefficients more than 30% lower than the typical silicon oxide SiO2 can be used. However, these organic polymers create etching problems because their chemical composition is close to that of the resin mask that is used to photo-etch the trenches. More specifically, the resin mask is removed by an isotropic etching in which the etching ions move in all directions. This can cause the organic polymer that serves as the dielectric to be impaired, or even etched. A similar problem results from the use of a dielectric made from an inorganic polymer whose surface becomes impaired so as to locally degrade the permittivity coefficient.
In view of these drawbacks, it is an object of the present invention to remove the above-mentioned drawbacks and to provide a Damascene-type process for manufacturing an integrated circuit using a dielectric having a low permittivity coefficient. According to the process, first and second stop layers are deposited on a first dielectric layer that covers a first metallization level, and the second stop layer is selectively etched with respect to the first stop layer. The first stop layer is selectively etched with respect to the first dielectric layer, a second dielectric layer is deposited on the circuit. The first and second dielectric layers are selectively etched with respect to the stop layers. In this manner, trenches are formed in the second dielectric layer and holes are formed in the first dielectric layer. Thus, a dielectric made of an organic or inorganic polymer having a low permittivity coefficient can be used without causing degradation, and low interline capacitances can be obtained.
In one preferred method, a third stop layer is deposited on the second dielectric layer. The third stop layer is selectively etched with respect to the second dielectric layer.
In one preferred method, after the trenches and holes are formed, metal is deposited in the holes and trenches to form the lines of a second metallization level and vias connecting the lines of first and second metallization levels. Then, the metal of the lines of the second metallization level is polished. In another preferred method, an encapsulation layer (e.g., of silicon nitride) is placed around the metal lines. The encapsulation layer is useful when the metal used for the lines is of a type that could diffuse into the dielectric. Such diffusion of metal (especially of copper or gold) into the dielectric would result in a decrease in the interline electrical isolation. The major risk is that the metallic contamination could reach the silicon substrate to create deep energy levels in the band gap of the semiconductor and increase the resistivity of the substrate.
Another object of the present invention is to provide an integrated circuit in which the dielectric layer is of a type that would conventionally be impaired by the etching process for removing the resin mask that is used to photo-etch the positions of the metallization lines. The integrated circuit includes at least first and second metallization levels that each include metallization lines separated by dielectric material. A dielectric layer is located between the two metallization levels and penetrated by vias that provide electrical connection between the metallization lines of the two metallization levels. A first stop layer, which is capable of being selectively etched with respect to the dielectric layer, is located between the dielectric layer and the second metallization level. Additionally, a second stop layer, which is capable of being selectively etched with respect to the first stop layer, is located above the first stop layer. The stop layers are provided because the mask used for photo-etching is of a similar nature to the polymers having a low permittivity coefficient, which are desirable (especially organic polymers) but would conventionally be impaired during removal of the mask.
Preferably, a third stop layer, which is capable of being selectively etched with respect to the dielectric material of the second metallization level, is located above the dielectric material of the second metallization level.
Accordingly, preferred embodiments of the present invention provide an integrated circuit that can have very small line widths and very small interline widths of dielectric material because the dielectric used has a low permittivity coefficient but is not degraded during the Damascene-type process for forming the circuit.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.